Device activating unit and cpu

ABSTRACT

A register circuit having a plurality of registers enabling the writing and reading of data by the specification of an address; a register controlling circuit monitoring data of a plurality of registers of the register circuit through the specification of an address, and writing, to a register pre-established in the register circuit, for activating devices; and a signal transmitting circuit causing a device to execute a specific operation, based on a specified address and on data read from the register circuit are provided; and not only is a collection of first bits for controlling jointly the individual operations of the plurality of devices assigned in a first register that is established in advance in the plurality of registers, but also second bits for controlling individually the individual operations in the plurality of devices are assigned respectively in a plurality of respective second registers that differ from the first register.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application claims priority under 35 U.S.C. §119 to JapanesePatent Application No. 2010-056525, filed Mar. 12, 2010, which isincorporated herein by reference,

FIELD OF TECHNOLOGY The present invention relates to a device activatingtechnology for activating a plurality of devices. BACKGROUND OF THEINVENTION

Substrate inspecting devices for inspecting substrates by capturingimages from a plurality of video cameras have been developed in order toinspect whether or not there are defects in manufactured products suchas substrates. For example, Japanese Unexamined Patent ApplicationPublication H6-222011 (“JP '011”) discloses a substrate inspectingdevice that uses a video signal that performs interlacing alternatingbetween odd frames and even frames. In this substrate inspecting device,horizontal synchronization signals that are offsetted by ½ thehorizontal synchronization period are applied to each of a set ofmutually-facing video cameras, where odd-frame images are captured byone video camera set, and even frame images are captured by the othervideo camera set. Doing so enables continuous and high-speed analysis ofinspection regions of manufactured products.

However, in the substrate inspecting device as set forth in JP '011, itis necessary to control the timing of the imaging in the plurality ofvideo cameras based on a synchronization signal. If an attempt were madeto control the timing of the activation of the individual video cameraswithout connections for supplying the synchronization signals, then timemeasuring means, such as a counter, would have to be used, and thetiming of activation would have to be controlled based on the countingvalue of the counter.

In activation control using such a counter, a register is assigned toeach device, and the control of the timing of activation for the devicesis performed based on the register counts. For example, after thecounter is activated, an operation is repeated wherein the number of thespecific register is changed each time a specific count elapses, tomeasure the passage of time, where the counting is ended when theregister count goes to zero, or the like, indicating that a specificamount of time has elapsed since the commencement of counting. Once thecounting of the elapsed time by the counter has ended, then this must bedetected without delay, and activating data must be written to theregister without delay to reactivate the counter.

However, because it is necessary for the reading and writing ofregisters by the controlling circuit to be performed sequentially foreach register, in some cases there will be a substantial delay in thetiming with which the data of the register is read after the registercount has reached zero. If the detection of the end of counting in anyof the counters is delayed, then the timing of the reactivation will belate, preventing the commencement of the image capturing from beingperformed with the correct timing.

Given this, one object of the present invention is to provide a devicecontrolling unit and CPU (central processing unit) able to operatewithout delay even when there is a plurality of devices that are notsynchronized to each other.

SUMMARY OF THE INVENTION

A device controlling unit according to the present invention, in orderto resolve the problem set forth above, is a device controlling unit forcontrolling at least a portion of operations of a plurality of devices,having:

a register circuit having a plurality of registers configured so as toenable writing and reading, of data by specifying an address;

a register controlling circuit for monitoring data of the plurality ofregisters of the register circuit, through specifying the address, andfor writing data to a register, determined in advance, of the registercircuit to activate a device; and

a signal transmitting circuit for causing one of the plurality ofdevices to perform a specific operation based on the specified addressand on data read out from the register circuit; wherein:

in the register circuit, a collection of first bits for controllingjointly the individual operations of the plurality of devices isassigned to a first register, established in advance in the plurality ofregisters, and second bits for controlling individually the individualoperations of the plurality of devices are respectively assigned to aplurality of respective second registers other than the first register.

In the invention above, while a shared first register is assigned forcontrolling the operations of a plurality of devices, individual secondregisters are also assigned for controlling the operations of individualdevices. Consequently, while it is possible to ascertain the operatingstate of any or all of the devices simultaneously by referencing thecollection of first bits in the first register, it is possible to startthe operation of individual devices with the respective timings bywriting data to a second bit in a corresponding second register for adevice that has ended its operation. Furthermore, operations of aplurality of devices can be started simultaneously by writing data to aplurality of first bits.

Forms such as the following can be applied to the present invention asdesired:

A device controlling unit as set forth above, wherein: the registercontrolling circuit writes, to a second bit of a second register thathas been assigned to a device, data commanding an operation of thedevice, when any of the collection of first bits of the first registerindicates that an operation of the device has ended.

A device controlling unit as set forth above, wherein the signaltransmitting circuit outputs a permission signal, for allowing theoperation of the device assigned to the second register, when data readfrom a second register, specified by a specified address, is data forcausing the operation of any of the plurality of devices.

A device controlling unit as set forth above, wherein: the signaltransmitting circuit writes, to a first bit of a first register that isassigned to a device that has ended an operation, data indicating theend of an operation of a device, when an operation of any of theplurality of devices has ended.

A device controlling unit as set forth above, wherein: a device is avideo camera, a counter, or a sequencer.

A device controlling unit as set forth above, wherein: the registercircuit uses at least a portion of bits other than bits used forcontrolling at least a portion of the operations of the plurality ofdevices as a counter for counting elapsed time from the beginning ofoperations of a plurality of devices.

A CPU that incorporates a device controlling unit as set forth above.

The present invention is provided with a first register for controllingjointly the operations of a plurality of devices, and second registersfor controlling individually the operations of the devices, thusenabling detection of the operating states of a plurality of deviceswithout delay, and enabling starting of the operations of a plurality ofdevices, either with individual timing or simultaneously.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a structural diagram of an inspecting device that includes adevice controlling unit according to an example.

FIG. 2 is a register structure diagram of a register circuit of theexample.

FIG. 3 is a structural diagram of a signal transmitting circuit of theexample.

FIG. 4 is a flowchart for explaining the operation of a registercontrolling circuit.

FIG. 5 is a flowchart for explaining the operation of the signaltransmitting circuit.

FIG. 6 is an example of an inconvenient method of use when using theregister.

FIG. 7 is an example of another inconvenient method of use when usingthe register.

FIG. 8 is a structural diagram of an inspecting device that includes adevice controlling unit of another example.

FIG. 9 is a register structure diagram for a register circuit accordingto a further example.

DETAILED DESCRIPTION OF THE INVENTION

Examples according to the present invention are explained below. In thedescriptions of the diagrams below, parts that are identical or similarare expressed by identical or similar codes. Note that the individualblocks described in the figures are described divided according tofunction, for convenience. Consequently, insofar as the desired effectof operation are obtained, the structure of the blocks described in thefigures may be used after appropriate modifications through designchanges. Additionally, each block structure may be embodied in hardware,or are means that may be embodied functionally through software.

The terminology used in the present invention is as defined below:

“Device” refers in general to devices that are subject to devicecontrol, including, for example, video cameras, counters, andsequencers.

“Data” refers to information that is expressed by a single bit thatstructures a register, but includes also cases indicating informationfor controlling a. single device using multiple bits. For example, the“data” will be “1” or “0”, expressed by a single bit, when controllingthe start Or end of an operation of a. device.

“Operation” refers to a process in the device, established in advance inaccordance with a specific objective. For example, when the device is avideo camera, the “operation” means capturing an image. If the device isa counter, then the “operation” refers to counting.

“Activate” is not limited to the narrow meaning of simply turning ON thepower of a device, but includes also causing a variety of functions tobe exhibited within the device.

“Control” is a concept that includes at least ascertaining the operatingstate of a device and starting a process by writing data to anappropriate bit.

“First Register” refers to a register for joint control of theoperations of a plurality of devices. The “first register” preferably isa single register by which the operations of a plurality of devices canbe controlled; however, in the event that the number of devices exceedsthe number of bits in a register, a plurality of registers can beassigned as “first registers.” The operating states of a plurality ofdevices can be ascertained simultaneously through referencing theplurality of bits in the “first register,” and the operations of aplurality of devices can be started simultaneously through writing datasimultaneously to a plurality of bits thereof.

“Second Register” refers to a register for controlling the operations ofa plurality of devices individually. An operation of an assigned deviceis started through writing the aforementioned “data,” established inadvance, to the “second register.” The operating states of thecorresponding device can be ascertained individually through referencingthe bit of the “second register” assigned to the device, and theoperation of the corresponding device can be started individuallythrough writing data to the bit that is assigned to the device.

“Simultaneously Operation Devices” refers to a plurality of devices forwhich the operations are to be started simultaneously. Any number ofdevices, numbering at least two, may be simultaneous operation devices.

An example according to the present invention relates to an inspectingdevice provided with a plurality of video cameras for performingpass/fail inspections on substrates, and the like, and, in particular,includes a device controlling unit according to the present invention,In the device controlling unit according to the first form ofembodiment, devices that are subject to operational control (videocameras) are assigned to individual bits of a first register for jointlycontrolling the operations, and also assigned to multiple secondregisters for controlling the operations of the devices individually.

FIG. 1 illustrates the structure of an inspecting device 1 according toan example. As illustrated in FIG. 1, the inspecting device 1 comprisesa plurality of video cameras 2, a device controlling unit 10, and animage memory 12.

A video camera 2 is an example of a device that is subject to theoperational control according to the present invention, and videocameras are provided in the same quantity (for example, eight videocameras) as the number of bits that structure a register in the registercircuit 100. Each individual video camera is also termed a “device x”(where x=A through H). Each individual video camera 2 is structured soas to capture, in frame units, images of an object being inspected (forexample, a substrate), and to send the image as image data to the imagememory 12 through the device controlling unit 10. For example, theplurality of video cameras 2 capture images of specific regions on thesubstrate with identical timing. The image data that is capturedsimultaneously is referenced by a. processing device, not shown, inorder to make mutual comparisons, for example. As a particularlydistinctive feature of the present invention, no wires are providedbetween the video cameras 2 to perform synchronization referencing asynchronization signal. Moreover, in the present form of embodiment, allof the plurality of video cameras 2 are assigned to “simultaneousoperation devices” in order to start the operation thereofsimultaneously.

The video memory 12 is structured so as to be able to update storagewherein the plurality of image data correspond to the individual videocameras 2. The video data stored in the video memory 12 can bereferenced by the processing device, not shown.

In the present invention, the device controlling unit 10 is providedwith a register circuit 100, a signal transmitting circuit 110, aregister controlling circuit 120, and a device controlling circuit 130.Of these, the register controlling circuit 120 is a central processingunit (CPU). The register circuit 100 and the signal transmitting circuit110 may be structured as a specialty integrated circuit (FPGA or ASIC).

The register circuit 100 has a plurality of registers that arestructured so that data can be written or read through the specificationof an address, In the register circuit 100, a particular register thatis determined in advance, from among the plurality of registers, isassigned as the “first register” for controlling jointly the operationsof a plurality of devices, Additionally, of the plurality of registers,the plurality of registers other than the first register is assigned as“second registers” for controlling the operations of the devicesindividually.

FIG. 2 illustrates the details of an example of assigning the registersof the register circuit 100 in the present form of embodiment. Asillustrated in FIG. 2, in this example the register circuit 100 isprovided with registers A through K that each are structured from eightbits (bit 7 through bit 0). The registers A through K are structured soas to be accessible, for example, by addresses 0x0000 through 0x0009. Ofthe registers A through K, register J (address 0x0008) is assigned asthe aforementioned first register, and registers A through the H areassigned as the aforementioned second registers. In the first registerJ, each of the bits, bit 7 through bit 0, are assigned as the collectionof “first bits” for starting the individual operations of the devices Athrough H. In the second registers A through H, bit 7 is assigned as a“second bit” for controlling the operations of the respective individualdevices A through H. Moreover, bit 6 in the second registers A through His assigned as a permission bit for enabling the individual devices.Furthermore, the six bits, bits 5 through 0 in the second registers Athrough H are used as counters for measuring the elapsed time from thebeginning of operations of the individual devices. For simplicity in thediscussion, the explanation regarding the permission will be omittedbelow. in particular, in the present example, the first register J isused in order to start the operations of a plurality of devicessimultaneously, Returning to FIG. 1, the register controlling circuit120 is structured so as to be able to monitor the data (the logicalstates of the bits) of the plurality of registers in the registercircuit 100 through the specification of an address, and so as to enablewriting of data (for example, the logical state “1” of the bit) in orderto start the operation of a device, Moreover, the register controllingcircuit 120 writes, to the second register that is assigned to theapplicable device, data to command the start of operation of that devicewhen the logical state of a first bit in the first register indicatesthat the operation of the device has ended. The register controllingcircuit 120 is embodied functionally, for example, through the executionof a software program on a central processing unit (CPU).

Specifically, the register controlling circuit 120 writes, to thecorresponding second register, data commanding the start of operation ofthe device (for example, bit logic “1,” both here and below) when any ofthe first bits in the first register J indicates the end of theoperation of the device (for example, when the bit logic is “0,” bothhere and below).

In particular, in the present example, all of the bits 7 through 0 thatstructure the first register J are assigned to “simultaneous operationdevices” (video cameras A through H) that are to start operationssimultaneously. Consequently, the register controlling circuit 120 isstructured so as to be able to write, to the first register J, data tostart the operation of the simultaneous operation devices when all ofthe bits 7 through 0 indicate that the operations have ended.

The signal transmitting circuit 110 is structured so as to be able tostart the operation of any device of the plurality of devices based on aspecified address and on data read out from the register circuit.Specifically, the signal transmitting circuit 110 reads out the data ofthe second bit of a second register that is specified by a specifiedaddress, and if the data that has been read out is data for starting theoperation of any of the plurality of devices, outputs a permissionsignal to enable the operation of the device assigned to the secondregister. Moreover, the signal transmitting circuit 110 is structured soas to be able to write data indicating the end of the operation of thedevice to both the corresponding first bit in the first register and thesecond bit of the second register that is assigned to a device that hasended its operations in the case that any device of the plurality ofdevices has ended its operation.

FIG. 3 illustrates a specific structure for a signal transmittingcircuit 110. As illustrated in FIG. 3, the signal transmitting circuit110 is provided with, for example, a selector circuit 112 and a datalatching circuit 114. These structures are diagrams that are illustratedschematically in order to explain the detection of the end of operationbased on data that is stored in the first register and explain theoutputting of the permission signal for enabling the start of operationof the device.

A selector circuit 112 and a data latching circuit 114 is provided foreach device, For simplicity in the discussion, FIG. 3 illustrates acombination of a selector circuit 112 for selecting the devicecorresponding to the second register E and the data latching circuit112. Actually, in the present example, the register circuit 100 isstructured so as to enable the selection of eight devices, and thusthere are eight sets of combinations of selector circuits 112 and datalatching circuits 114, matching the number of devices that can heselected.

The register controlling circuit 120 outputs, onto an address bus Abusan address for accessing one of the registers of the register circuit100. The data of the register read out by the access by the registercontrolling circuit 120 is outputted onto a data bus Dbus.

The selector circuit 112 is provided with, for example, AND gates 1120and 1122, and an OR gate 1124. The AND gate 1120 of the selector circuit112 is structured so as to output the data value of the first bit (bit 3in register J) when the first register J is accessed (address 0x0008).The AND gate 1122 of the selector circuit 112 is structured so as tooutput the data value of the second bit (bit 7 in register E) when thesecond register is accessed (address 0x0004). The OR gate 1124 isstructured so as to output the logical sum of the outputs of the ANDgate 1120 and the AND gate 1122.

The data latching circuit 114 is structured from a data latch or aflip-flop. The data latching circuit 114 latches the output data Data ofthe selector circuit 112 with the timing of a load signal Load outputtedby the register controlling circuit 120. Following this, the output dataData is outputted as a permission signal Run for the individual devicewhen an enable signal Enable is outputted, for the device correspondingto the activation register E, from the register controlling circuit 120.

Outputs are enabled matching the permission timing for each device, foreither the activation data of the register that has been set as thesimultaneous activation register or the register that has been set asthe individual activation register, through the selector circuit 112 andthe data latching circuit 114.

Additionally, upon receipt, from the device controlling circuit 130, ofa notification to the extent that any of the devices has ended itsoperation, the signal transmitting circuit 110 writes end-of-operationdata, indicating the end of an operation of a device, to a monitoringregister that is assigned to the device that has ended the operation.The signal transmitting circuit 110 also writes end-of-operation data,indicating the end of the operation of the device, to data for theactivating register corresponding to the device that has ended theoperation, provided separately from the monitoring register. In thepresent example, if, for example, the device E has ended its operation,then bit 3 of the selecting first register J is reset (written with thebit logic “0”), and bit 7 of the corresponding activating secondregister F is also reset. The resetting of the registers by the signaltransmitting circuit 110 is preferably achieved in hardware. This isbecause doing so in a hardware process makes it possible to reflect theend of the operation of the device as data, without delay, to theregister upon the end of the operation by the device.

Upon reception of a permission signal Run for a device from the devicecontrolling device 10, the device controlling circuit 130 activates thecorresponding device. When image data is provided from the correspondingdevice, the device controlling circuit 130 forwards that image data tothe image memory 12. When the transfer of the image data from thecorresponding device has ended, then the device controlling circuit 130provides the signal transmitting circuit 110 with a notification thatthe operation of the device has ended.

For ease in understanding the benefits of the present invention, theproblem areas in the controlling activation through a register areexplained based on FIGS. 6 and FIG. 7.

In a device controlling unit wherein dedicated synchronizationconnection lines for synchronizing the devices are not provided, thecontrolling circuit (CPU) monitors the end of operation of the devices,and performs control so as to start the operations of the devices.Typically, one may consider controlling devices through registers thatthe controlling circuit controls directly. As methods wherein registersare used, there is a. method wherein devices are assigned correspondingto registers, and a method wherein devices are assigned corresponding toindividual bits of a single register.

FIG. 6 is a register assignment diagram for explaining a method. Asillustrated in FIG. 6, in this method, devices A through H are assignedcorresponding to the respective registers A through H, and theindividual registers are used as registers for starting the operationsof the devices and as registers for monitoring the states of operationof the devices.

When monitoring the end of operations of the individual devices, thesame bit as the bit that is written with the activation data(hereinafter termed the “control bit”) of a register, corresponding tothe device that is subject to monitoring, is referenced, When theoperation of an individual device has ended, then end-of-operation data(for example, the bit logic of “0”), indicating that the operation hasended, is written to the control bit of the register that is assigned tothe device, the register controlling circuit monitors the control bit ofthe register that is assigned to the device that is subject tomonitoring. When the end-of-operation data is written, processing thenmoves to the next process, such as writing activation data in order toreactivate.

On the other hand, when activating each individual device individually,activation data (for example, bit logic “1”) that commands activation iswritten to the control bit of the register to which the activation datais to be written (for example, bit 7) that is assigned to the devicethat is to be activated. When activation data is written, activationdata is outputted to the device controlling circuit from the signaltransmitting circuit, structured as in FIG. 3, above, to activate thedevice that is to be activated.

The method described above makes it possible to activate devicesindividually with arbitrary timing. However, on the other hand, theregisters must be accessed sequentially, and thus it is not possible todetect immediately the end of operations of a plurality of devices. Thisresults also in a shortcoming that is not possible to activate aplurality of devices simultaneously.

For example, if, in FIG. 6, the register E at address 0x0004 is read andthe control bit (bit 7) is at the end-of-operation data “0”, then theconclusion is drawn that the operation of the device F has ended, andthe device can be reactivated by writing an activation data “1” to thissame control bit (bit 7). Here there is a possibility that during thisprocess other devices end the operations thereof later. However, if, inthe first method, the control bits of the registers are not referencedsequentially, then it would not be possible to detect the end ofoperations of the respective devices. Additionally, even if it weredetermined that there is another device wherein the operation thereofended at essentially the same time, it would not be possible to activatethat other device by writing activation data to the control bit of theregister corresponding to that other device until after device E hasbeen activated first.

FIG. 7 is a diagram of the register assignments for explaining anothermethod. As indicated in FIG. 7, in this method, all of the devices Athrough H are assigned to a single register J, and the individual bitsin the register are assigned as control bits for starting the operationsof the corresponding devices and for detecting the operating states ofthe corresponding devices.

The data of the control bits of the register are read in and referencedto detect the end of operations of the individual devices. When theoperations of the individual devices have ended, an end-of-operationdata (for example, bit logic “0”) that indicates the end of theoperation is written to the control bit that is assigned to the devicethat is being monitored. The register controlling circuit references thecontrol bit that is assigned to the device that is being monitored. Ifthe end-of-operation data “0” is written to the control bit, then it canbe confirmed that the device that is being monitored has ended itsoperation.

On the other hand, when activating the device, data for starting theactivation (for example, bit logic “1”) is written to the control bitthat is assigned to the device to be activated. Normally, the registercannot be written by the bit unit, and thus activating data (forexample, the bit logic “1”) for starting operations is writtensimultaneously to the control bits assigned to other devices as well.This is not a problem if all of the devices other than the device thatis being activated are already operating. Activating data may be writtenthat causes the bit logic for the control bits other than the controlbit corresponding to the device to be activated to go to “1”, Whenactivating data is written to any of the control bits, then activatingdata is outputted to the device controlling circuit by the signaltransmitting circuit that is structured as in FIG. 3, above,reactivating the device that is being activated. The operating statedoes not change for any device that is already operating.

In the second method set forth above, the ends of operations of aplurality of devices can be detected simultaneously by writingend-of-operation data to a plurality of control bits simultaneously.However, in most cases the starting and ending timings of the deviceswill differ, meaning that the control bits corresponding to the otherdevices, with different timings, will be changed into end-of-operationdata. In an unfortunate event, the entire register may be written withactivating data, because of a device for which the end of operation hasalready been detected, prior to one of the control bits being changed tothe end-of-operation data. That is, events may move forward in asequence wherein a first device completes its operation, followed by thedetection of the end of operation of the first device through areference to the control bit corresponding to the first device, followedby the end of the operation by a second device, followed by anactivation command to the control bit corresponding to the first device,followed by the detection of the end of operation of the second deviceby referencing the control bit corresponding to the second device. Inthis case, the control bit that has been changed to the end-of-operationdata (for example, bit logic “0”) will be overwritten by the activatingdata (for example, bit logic “1”). overwritten, then the end of theoperation of the device is not detected.

Additionally, even when there is a plurality of devices that have endedtheir operations, it is not possible to activate a plurality of deviceswith individually differing timings, without commanding simultaneousactivation by writing the activating data all at once. In FIG. 7, forexample, if the register J at address 00x0008 is read and the controlbit (bit 3) is the end-of-operation data “0”, then it can be concludedthat the operation of device E has ended. If the other control bits(other than bit 3) are not the end-of-operation data, it can beconcluded that the only device that has ended its operation is device E,and thus device E is reactivated by writing the data. 0xF F (wherein allbits are “1”) to register J. However, if the operation of another deviceis ended during this reactivating process, than, as described above, itis not possible to detect the end of that operation. Furthermore, it isnot possible to start the devices A through H, which are assigned to theregister J, individually, with different timings.

Basically, while it is possible to use the method, set forth above, toactivate the plurality of devices with different timings, there is theshortcoming that it is not possible to monitor the operating states ofthe plurality of devices simultaneously. On the other hand, while it ispossible to use the other method, set forth above, to monitor theoperating states of the plurality of devices simultaneously, and toactivate the plurality of devices simultaneously, there is a shortcomingin that it is not possible to activate the individual devices withdifferent timings.

The operation in the present example is explained next. As describedabove, the register circuit 100 has the following distinctive features:

A specific register J, determined in advance from among the plurality ofregisters A through K is assigned as a first register for controllingjointly the operations of the plurality of devices A through H;

Registers A through H, other than the first register J, are assigned assecond registers for controlling individually the plurality of devices Athrough H; and

Of the plurality of devices A through H, simultaneous operation devicesA through H are all assigned to the first register J.

Moreover, if any of the group of first bits (bits 7 through 0) of thefirst register J indicates the end of the operation of a device (forexample, a bit logic “0”), the register controlling circuit 120 writesactivating data (for example, bit logic “1”) for commanding theactivation of the device to the second bit of the second register Athrough H that is assigned to the device for which the operation hasended. Moreover, if a plurality of first bits of the first register Jall indicate ends of operations (for example, bit logic “0”), then theregister controlling circuit 120 writes, to the plurality of first bits,the activating data (for example, 0xFF) that commands the simultaneousactivation of the simultaneous operation devices A through H.

The register controlling method according to an example that uses theregister circuit 100, structured as set forth above, is explained nextin reference to the flow chart in FIG. 4. The flow chart in FIG. 4 isfor explaining a process that is executed by the register controllingcircuit 120, which is achieved through execution of a software programby the register controlling circuit 120, which is a CPU.

In Step S1, the register controlling circuit 120 reads the data. of thefirst register J of the register circuit 100. For this process, address0x0008 is outputted to the address bus Abus, and data reflecting theoperating states of the devices A through H is outputted to the data busDbus. Following this, processing advances to Step S2, wherein theregister controlling circuit 120 evaluates whether or not there is anyfirst bit in the first register J that is the end-of-operation data(which here is bit logic “0”). If the result is that there is noend-of-operation data included in the data outputted from the firstregister J (NO), then processing returns again to the process formonitoring the first register J (S1).

If, in Step S2, end-of-operation data is included in the output datafrom the first register J (YES), then processing advances to Step S3,and an evaluation is made as to whether or not the device that isassigned to the first bit for which the data was end-of-operation datahas been set in advance as a simultaneous activation device. If it hasbeen set as a simultaneous operation device (YES), then processingadvances to Step S4, and an evaluation is performed as to whether or notall of the first bits corresponding to the other devices that are set asthe simultaneous activation devices have changed to end-of-operationdata. If the result is that there is a device, among the devices set assimultaneous activation devices, for which the data has not been set tothe end-of-operation data (NO), then processing awaits the data for allof the simultaneous activation devices becoming end-of-operation data.

If all of the first bits corresponding to the devices that are set assimultaneous activation devices have changed to end-of-operation data(YES), processing advances to Step S5, and the register controllingcircuit 120 writes activating data (which here is bit logic “1”) both tothe first bits corresponding to the simultaneous activation devices inthe first register and the second bits, of the plurality of secondregisters, corresponding to the simultaneous activation devices. Thatis, address 0x008 is outputted to the address bus Abus, and data 0XFF iswritten through the data bus Dbus to the first register J. Processingthen goes to the process for reading the first register (S1).

On the other hand, in Step S2, if the device that is assigned to thefirst bit that has changed to the end-of-operation data in the firstregister is not a simultaneous activation device (NO), then it isdetermined that the device to be activated is an individual activationdevice. Given this, processing advances to Step S5, and the registercontrolling circuit 120 writes activating data to the second bit of thesecond register that is assigned to the device that is to be activated.In the case wherein the second device is device E, for example, then0x0004 is outputted to the address bus Abus, the second register E isaccessed, and activation data (which here is bit logic “1”) is writtento the second bit (at least to bit 7).

The process for writing end-of-operation data to the register circuit100 is explained next in reference to the flow chart in FIG. 5. The flowchart in FIG. 5 illustrates a process that the signal transmittingcircuit 110 executes in hardware, executed instantly through logic.

If, in Step S11, a permission signal Run is outputted from the datalatching circuit 114 (YES), then, in the device controlling circuit 130,the device corresponding to the permission signal Run is activated(S12).

On the other hand, if, in Step S13, the end of operation of acorresponding device is detected by the signal transmitting circuit 110through the device controlling circuit 130 (YES), then the signaltransmitting circuit 110 changes the corresponding first bit in thefirst register J to the end-of-operation data (which here is bit logic“0”). Similarly, the second bit of the second register assigned to thedevice wherein the operation has ended is also changed to theend-of-operation data.

(1) In this example, a first register J for controlling jointly theoperations of a plurality of devices A through H is assigned, and secondregisters A through H for controlling individually the operations of theplurality of devices A through H are assigned as well. As a result,while it is possible to discern the operating states for all of thesedevices simultaneously through referencing the first register J, it isalso possible to start the operation of an individual device promptlythrough the use of an individual second register A through H thatcorresponds to a device wherein the operation has ended.

(2) Given the example, in the register circuit 100 register J isassigned as the first register for simultaneous operation devices Athrough H, making it possible to start simultaneously the operations ofthe simultaneous operation devices A through H through writingactivation data all at once to the first bits of the first register J.

(3) Given the example, if data that is read out from a second registerthat is specified by a specified address is activation data foractivating any of the plurality of devices A through H, then the signaltransmitting circuit 110 outputs a permission signal Run that enablesthe operation of the device assigned to the second register. Thisenables the easy activation of a device through writing activating datato the second register to which the device to be activated is assigned.

(4) In the example, if the operation has ended for any of the pluralityof devices A through H, the signal transmitting circuit 110 changes, toend-of-operation data, the first bit in the first register that has beenassigned to the device wherein the operation has ended. This enables thedetection of the device operating state by reading the data of the firstbit of the first device.

Another example according to the present invention relates to in thesame inspecting device as in the above example, the structure pertainingto the device controlling unit is a CPU (central processing unit) thathas been integrated into a single-chip substrate. Those structuralelements that are identical to those set forth above, are assignedidentical codes, and explanations thereof are omitted.

FIG. 8 illustrates the structure of the inspecting device 1 as set forthin the present example. As illustrated in FIG. 8, the inspecting device1 b includes a plurality of video cameras 2; an image reading circuit 3;a device controlling unit 10 b, and an image memory 12.

The image reading circuit 3 is structured so as to be able to read imagedata from each of the plurality of video cameras 2, and so as to be ableto send this image data to the image memory 12. Additionally, it isstructured so as to be able to provide a notification to the devicecontrolling circuit 130 that the reading of the image data has ended.

In the present example, the difference from the aforementioned exampleis, specifically, the point that the device controlling unit 10 b isstructured by integrating the register circuit 100, the signaltransmitting circuit 110, the register controlling circuit 120, and thedevice controlling circuit 130 into a single substrate (for example, asemiconductor substrate). The functions of the individual circuits areas described above.

As described above, the device controlling device 10 b is not onlystructured from individual components, but, as in the present example,can be structured as a CPU that is integrated into a single chip.

A further example according to the present invention has a distinctivefeature in the point that a plurality of first registers is provided,assigned to different register circuits, in a structure that is similarto that of the above example.

The present example differs from the examples described above, in thepoint that the register circuit 100 is assigned as illustrated in FIG.9. The other structures are as described above, and explanations thereofare omitted.

FIG. 9 illustrates the details of the register assignments in theregister circuit 100 b in the present example. As illustrated in FIG. 9,the register circuit 100 b is provided with, for example, registers Athrough M, each comprising eight bits. The registers A through M arestructured so as to be accessible by, for example, the addresses 0x0000through 0x00B. Of the registers A through M, register J (address 0x0008)is assigned as the first register (1), register K (address 00x0009) isassigned as the first register (2), register L (address 0x000A.) isassigned as the first register (3), and register M (address 0x000B) isassigned as the first register (4). The registers A through H beingassigned as second registers is identical to the case described above.

In the first register (1) J, bit 7 through bit 4 are all assigned as acollection of first bits for detecting the operating states of a deviceA, a device B, a device C, and a device D. The first register (1) J isalso a register for the simultaneous activation of the device A, deviceB, device C, and device D.

In the first register (2) K, bit 7 through bit 4 are all assigned as acollection of first bits for detecting the operating states of a deviceE, a device F, a device G, and a device H. The first register (2) K isalso a register for the simultaneous activation of the device E, thedevice F, the device G, and the device H.

In the first register (3) L, bit 7 through hit 4 are all assigned as acollection of first bits for detecting the operating states of thedevice A, the device B, the device G, and the device H. The firstregister (3) F is also a register for the simultaneous activation of thedevice A, the device B, the device G, and the device H.

In the first register (4) M, bit 7 through bit 4 are all assigned as acollection of first bits for detecting the operating states of a deviceE, a device F, a device C, and a device D. The first register (4) M isalso a register for the simultaneous activation of the device F, thedevice F, the device C, and the device D.

The register circuit 100 b is structured as described above, thusenabling control by the register controlling circuit 120 as follows inthe present third form of embodiment:

(1) To activate the individual devices A through H with individualtimings, activation data is written to the individual second bits (bit7) of the second registers A through H, Doing so enables the devices Athrough H that correspond to the second registers A through H, to whichthe activation data has been written, to be activated with arbitrarytiming.

(2) If the device A, the device B, the device C, and the device D are tobe activated simultaneously, then the activation data is written to thecollection of first bits (bit 7 through 4) of the first register (1) J.The device A, the device B, the device C, and the device D can beactivated simultaneously by writing activation data to the collection offirst bits in the first register (1) J.

(3) If the device E, the device F, the device G, and the device H are tobe activated simultaneously, then the activation data is written to thecollection of first bits (bit 7 through 4) of the first register K. Thedevice E, the device F, the device G, and the device ii can be activatedsimultaneously by writing activation data to the collection of firstbits in the first register (2) K.

(4) If the device A, the device B, the device G, and the device H are tobe activated simultaneously, then the activation data is written to thecollection of first bits (bit 7 through 4) of the first register (3) L.The device A, the device B, the device G, and the device H can beactivated simultaneously by writing activation data to the collection offirst bits in the first register (3) L.

(5) If the device E, the device F, the device C, and the device are tobe activated simultaneously, then the activation data is written to thecollection of first bits (bit 7 through 4) of the first register (4) M.The device E, the device F, the device C, and the device D can beactivated simultaneously by writing activation data to the collection offirst bits in the first register (4) M.

In the above, the example provides a plurality of first registers, thusenabling not only the same effects of operation as is described above,but also enabling the combination of devices that are activatedsimultaneously to be selected and changed for each operation. Thisenables richer device operation control.

The present invention is not limited to the example set forth above, butrather can be modified as appropriate in a variety of ways in a rangethat produces the effects of operation of the present invention.

For example, white in the example set forth above, all eight deviceswere simultaneous activation devices, and in the further example setforth above, four devices were set as simultaneous activation devices,there is no limitation thereto, but rather devices of an arbitrarynumber not less than two can be used as simultaneous activation devices.

In the examples set forth above, the activating data and theend-of-operation data were both illustrated as single-bit data; however,there is no limitation thereto, and multiple bits may correspond to asingle control data. Having multiple bits correspond to a single controldata enables monitoring of three or more device operating states, andenables control of three or more different operations. For example, ifthe control data comprises 2 bits, that along with “activate” and“end-of-operation”, for the operations, operating states such as“standby” and “N/A (no device)” can be monitored and these operationscan be controlled, etc.

The device controlling unit according to the present invention can beapplied to circuits and devices wherein device operations are controlledthrough registers.

1. A device controlling unit for controlling at least a portion ofoperations of a plurality of devices, comprising: a register circuithaving a plurality of registers configured so as to enable writing andreading of data by specifying an address; a register controlling circuitmonitoring data of the plurality of registers of the register circuit,through specifying the address, and writing data to a register,determined in advance, of the register circuit to activate a device; anda signal transmitting circuit causing one of the plurality of devices toperform a specific operation based on the specified address and on dataread out from the register circuit; wherein: in the register circuit, acollection of first bits for controlling jointly the individualoperations of the plurality of devices is assigned to a first register,established in advance in the plurality of registers, and second bitsfor controlling individually the individual operations of the pluralityof devices are respectively assigned to a plurality of respective secondregisters other than the first register.
 2. The device controlling unitas set forth in claim 1, wherein: the register controlling devicewrites, to a second bit of a second register that has been assigned to adevice, data commanding an operation of the device, when any of thecollection of first bits of the first register indicates that anoperation of the device has ended.
 3. The device controlling unit as setforth in claim 1, wherein: the signal transmitting circuit outputs apermission signal allowing the operation of the device assigned to thesecond register, when data read from a second register, specified by aspecified address, is data causing the operation of any of the pluralityof devices.
 4. The device controlling unit as set forth in claim 1,above, wherein: the signal transmitting circuit writes, to a first bitof a first register that is assigned to a device that has ended anoperation, data indicating the end of an operation of a device, when anoperation of any of the plurality of devices has ended.
 5. The devicecontrolling unit as set forth in claim 1, wherein: a device is a videocamera, a counter, or a sequencer.
 6. The device controlling unit as setforth in claim 1, wherein: the register circuit uses at least a portionof bits other than bits used for controlling at least a portion of theoperations of the plurality of devices as a counter for counting elapsedtime from the beginning of operations of a plurality of devices.
 7. ACPU that incorporates a device controlling unit as set forth in claim 1.